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A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade
Stockholm University, Faculty of Science, Department of Physics. Lawrence Berkeley National Laboratory, USA.
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Number of Authors: 152019 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 14, article id C07005Article in journal (Refereed) Published
Abstract [en]

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.

Place, publisher, year, edition, pages
2019. Vol. 14, article id C07005
Keywords [en]
Analogue electronic circuits, Data acquisition circuits, Front-end electronics for detector readout, VLSI circuits
National Category
Physical Sciences
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-172017DOI: 10.1088/1748-0221/14/07/C07005ISI: 000474820400003OAI: oai:DiVA.org:su-172017DiVA, id: diva2:1346644
Conference
9th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL), Taipei, Taiwan, December 10-14, 2018
Available from: 2019-08-28 Created: 2019-08-28 Last updated: 2019-11-01Bibliographically approved
In thesis
1. Performance Improvements for Particle Tracking Detectors in Extreme Rate and Radiation Environments
Open this publication in new window or tab >>Performance Improvements for Particle Tracking Detectors in Extreme Rate and Radiation Environments
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In order to increase its discovery potential, the Large Hadron Collider (LHC) at CERN is being transformed into a higher luminosity machine expected to be operational around 2026. The number of particle collisions will increase by a factor of 10 beyond the current design value, which means that the detectors installed around the LHC are facing various new challenges. The most demanding challenges include handling the enormous data quantities that will be transferred from the front-end readout modules at significantly higher rates than previously, as well as the radiation effects that arise as a consequence of the intense particle flow and that cause damage to sensor elements and electronics.

At the ATLAS experiment, a multipurpose detector operating at the LHC, the impact of the luminosity increase is especially severe for the silicon pixel tracking detector, being the central subsystem located closest to the particle interaction point and therefore exposed to the highest radiation dose and hit density. The extreme radiation doses that the pixel modules will be subject to will cause deformation of the sensor material structure and thus loss of the signals, which after subsequent digitization by the pixel readout chip must be transferred over relatively long distances through a low-mass data link, causing further signal distortion.

The work presented here addresses both major challenges described and outlines solutions for the upcoming upgrade of the ATLAS pixel detector system with regards to these. Firstly, it is demonstrated how improved accuracy of detector simulations and reconstruction of particle trajectories through the detector can be achieved as higher particle fluences are approached, by modeling radiation damage effects that occur in the pixel sensors. Secondly, it is shown how a receiver integrated circuit utilizing an industry standard technique novel within high-energy physics applications has been designed as an integral part of a high-speed transmission link to efficiently restore the signal quality in order to achieve adequate data readout rates.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm University, 2019. p. 99
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175161 (URN)978-91-7797-909-8 (ISBN)978-91-7797-910-4 (ISBN)
Public defence
2019-11-29, sal FB54, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 13:00 (English)
Opponent
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Available from: 2019-11-06 Created: 2019-10-15 Last updated: 2019-11-01Bibliographically approved

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