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Redesign of the ATLAS Tile Calorimeter read-out link and control board for the high-luminosity LHC era
Stockholm University, Faculty of Science, Department of Physics.ORCID iD: 0000-0001-9931-2896
Stockholm University, Faculty of Science, Department of Physics.
Stockholm University, Faculty of Science, Department of Physics.
Stockholm University, Faculty of Science, Department of Physics.
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2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

The R&D for the new on-detector electronics for the Phase-II ATLAS upgrade for the High-Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) Daughterboard (DB). The DB is the read-out link and control board interface to the off-detector electronics of TileCal. The DB receives configuration commands and LHC timing via two CERN radiation-hard GBTx ASICs and two redundant 4.8 Gbps downlinks. Two Ultrascale+ FPGAs send continuous high-speed read-out of digitized Photomultiplier Tube (PMT) samples through four 9.6 Gbps uplinks. We present a DB redesign that improves the timing scheme, and enhances the radiation tolerance by mitigating Single Event Latch-up (SEL) induced errors and implementing a more robust power-up and current monitoring scheme. The design minimizes single points of failure and reduces sensitivity to Single Event Upsets (SEUs) and radiation damage by employing a double-redundant scheme, using Triple Mode Redundancy (TMR) and Xilinx Soft Error Mitigation (SEM) in the FPGAs, adopting Cyclic Redundancy Check (CRC) error verification in the uplinks and Forward Error Correction (FEC) in the downlinks.

Place, publisher, year, edition, pages
2019.
Keywords [en]
hl lhc, radiation tolerant, daughterboard, tilecal, phase-ii upgrade, tid, niel, see, seu, xilinx, ultrascale, ultrascale+, fpga, gbtx
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-175371OAI: oai:DiVA.org:su-175371DiVA, id: diva2:1363190
Conference
The 17th Biennial International Conference on Accelerator and Large Experimental Physics Control Systems, New York, USA, 5 - 11 October, 2019
Available from: 2019-10-22 Created: 2019-10-22 Last updated: 2019-11-12
In thesis
1. Development of the read-out link and control board for the ATLAS Tile Calorimeter Upgrade
Open this publication in new window or tab >>Development of the read-out link and control board for the ATLAS Tile Calorimeter Upgrade
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The Phase-II upgrade plan for the ATLAS Hadronic Tile Calorimeter facing the High-Luminosity LHC (HL-LHC) era includes approximately 1000 radiation tolerant read-out link and control boards (Daughterboards) that will provide full-granularity digital data to a fully-digital trigger system off-detector through multi-Gbps optic fibres. Different Daughterboard (DB) revisions have been developed, each successively aiming to meet the demanding HL-LHC requirements. The DB communicates with the off-detector systems via four 9.6 Gbps uplinks and two 4.8 Gbps downlinks. The DB performs high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC-synchronous timing to the front-end system. The design aims to minimize radiation-induced errors and enhance data reliability by embracing a fully double redundant design using CERN radiation hard GBTx ASICs and Xilinx FPGAs, implementing Triple Mode Redundancy (TMR), adopting Soft Error Mitigation (SEM) to correct for configuration memory Single Event Upsets (SEU), and employing Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) in the data format of the uplink and downlink, respectively. Total Ionizing Dose (TID), Non-Ionizing Energy Losses (NIEL) and Single Event Effects (SEE) radiation tests have been performed in order to assess the radiation tolerance strategies followed in the design and to qualify the DB for the HL-LHC requirements according to the ATLAS policy on radiation tolerant electronics. This thesis presents the author's contribution to the development of the DB through the different revisions, the integration of the DB to the Demonstrator and the radiation tests performed aiming to demonstrate the readiness of the DB to withstand the radiation requirements imposed by the HL-LHC. Resulting of this document, the author proposes strategies to be used in the new DB design moving forward the final design to be produced and inserted in ATLAS during the 2024-2026 period.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm University, 2019. p. 97
Keywords
HL-LHC, ATLAS, Tile Calorimeter, TileCal, Demonstrator, Daughterboard, Read-out, Digital electronics, Data acquisition, Radiation tolerant, GBTx, TID, NIEL, SEU, SEL, FPGA, Kintex 7, Ultrascale, Ultrascale+, Optic Links
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-175246 (URN)978-91-7797-895-4 (ISBN)978-91-7797-896-1 (ISBN)
Public defence
2019-12-10, sal FB54, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 09:00 (English)
Opponent
Supervisors
Available from: 2019-11-15 Created: 2019-10-22 Last updated: 2019-11-12Bibliographically approved

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