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A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC.
Stockholm University, Faculty of Science, Department of Physics.ORCID iD: 0000-0001-9931-2896
Stockholm University, Faculty of Science, Department of Physics.ORCID iD: 0000-0001-7734-7617
Stockholm University, Faculty of Science, Department of Physics.
Stockholm University, Faculty of Science, Department of Physics.
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2021 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 68, no 9, p. 2414-2420Article in journal (Refereed) Published
Abstract [en]

The ATLAS Tile Calorimeter (TileCal) readout link and control Daughter Board (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity Large Hadron Collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bi-directional fiber optic links. Two CERN-developed, radiation hard GBTx ASICs receive LHC timing signals and configuration commands through 4.8 Gbps downlinks, which are in turn propagated to the front-end through Xilinx Kintex Ultrascale FPGAs. The Kintex FPGAs also continuously perform real-time readout and transmission of digitized Photomultiplier (PMT) samples, Detector Control System signals and monitoring data through redundant pairs of 9.6 Gbps uplinks. The DB design aims at minimizing single points of failure, and improving performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified Commercial off-the-shelf (COTS) components. Mitigation of radiation-induced Single Event Upsets (SEU) in the FPGAs is performed by a combination of the Xilinx Soft Error Mitigation (SEM) utility and Triple Mode Redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through Forward Error Correction (FEC) in the downlinks and Cyclic Redundancy Check (CRC) error verification in the redundant uplinks. This paper presents the latest revision of the DB (version 6), a redesign that addresses Single Event Latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the ADC read-out, and improved timing performance.

Place, publisher, year, edition, pages
2021. Vol. 68, no 9, p. 2414-2420
Keywords [en]
link hub, Single Event Latchup, Single Event Effects, Non Ionizing Energy Losses, Triple Mode Redundancy
National Category
Subatomic Physics
Identifiers
URN: urn:nbn:se:su:diva-195448DOI: 10.1109/TNS.2021.3103408ISI: 000697227000012OAI: oai:DiVA.org:su-195448DiVA, id: diva2:1585734
Available from: 2021-08-17 Created: 2021-08-17 Last updated: 2025-02-14Bibliographically approved
In thesis
1. Design of the HIBEAM/NNBAR Calorimeter and Upgrades to the ATLAS Tile Calorimeter Readout Electronics
Open this publication in new window or tab >>Design of the HIBEAM/NNBAR Calorimeter and Upgrades to the ATLAS Tile Calorimeter Readout Electronics
2023 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The Standard Model has been greatly successful in predicting the laws that govern our universe. Yet there are still seemingly missing pieces to the model. Detector development plays a crucial role in advancing our understanding of particle physics and helps answer some of the most pressing questions in the field, such as the nature of dark matter and why a matter-antimatter asymmetry is observed. This thesis has covered the work of developing detectors for two different experiments.

The HIBEAM/NNBAR experimental program will be a search after neutron-sterile neutron and neutron-antineutron oscillations housed in the the European Spallation Source (ESS) in Lund, Sweden. The experiment will reach unprecedented sensitivity for free-neutron searches, surpassing the last the oscillation time limit by 3 orders of magnitude. This thesis presents an overview of the experimental goals and the opportunities afforded by the ESS infrastructure. The primary work for this thesis has been the design, simulation and construction of a prototype calorimeter for NNBAR stage of the experiment, which is presented here.

The ATLAS experiment is currently undergoing upgrades to meet the requirements of the high-luminosity, high-radiation environment at the HL-LHC. This thesis provides an overview of the LHC and the ATLAS experiment, with special focus on the hadronic Tile calorimeter. TileCal will be upgraded to provide full granularity data at the lowest trigger level of the upgraded ATLAS trigger and data acquisition system. The work presented here focuses on TileCal upgrades to Daughterboard (DB), the interlink board responsible for the management of on- and off-detector data transmission. This work has been primarily focused on the design and fabrication of two printed circuit boards to test the implementation of a commercial, radiation-hardened FPGA in the upgraded DB design. The FPGA will control access to remote control JTAG in the DB Xilinx FPGA interface. 

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm University, 2023
National Category
Subatomic Physics Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-217205 (URN)
Presentation
2023-06-09, B4:1059, 16:23 (English)
Opponent
Supervisors
Available from: 2023-05-22 Created: 2023-05-19 Last updated: 2023-05-22Bibliographically approved

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Valdes Santurio, EduardoSilverstein, SamuelBohm, ChristianDunne, KatherineLee, SuhyunMotzkau, Holger

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