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FPGA-based Instrumentation for Advanced Physics Experiments
Stockholm University, Faculty of Science, Department of Physics. (System and Instrumentation Physics)
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Modern physical experiments often demand advanced instrumentation based on advances in  technology. This work describes four instrumentation physics projects that are based on modern, high-capacity Field-Programmable Gate Arrays, making use of their versatility, programmability, high bandwidth communication interfaces and signal processing capabilities.

In the first project, a jet-finding algorithm for the ATLAS detector at the LHC experiment at CERN was developed and implemented, and different verification methods were created to validate the functionality and reliability. The experiment uses a three level trigger system, where the first level uses custom FPGA-based hardware for analysis of collision events in real-time.

The second project was an advanced timing and triggering distribution system for the new European X-Ray Free Electron Laser (XFEL) facility at DESY in Hamburg. XFEL will enable scientists to study nano structures on the atomic scale. Its laser pulses will have the strongest peak power in the world with extremely short duration and a high repetition rate, which will even allow filming of chemical reactions. The timing system uses modern FPGAs to distribute high-speed signals over optical fibers and to deliver clocks and triggers with high accuracy.

The third project was a new data acquisition board based on high-speed ADCs combined with high-performance FPGAs, to process data from segmented Ge-detectors in real-time. The aim was to improve system performance by greatly oversampling and filtering the analog signals to achieve greater effective resolution.

Finally, an innovative solution was developed to replace an aging system used at CERN and Stockholm University to test vital electronics in the Tile Calorimeters of the ATLAS detector system. The new system is entirely based on a commercial FPGA development board, where all necessary custom communication protocols were implemented in firmware to emulate obsolete hardware.

Abstract [sv]

Inom området instrumenteringsfysik bedrivs forskning och utveckling av avancerade instrument, som används inom moderna fysikexperiment. Denna avhandling beskriver fyra projekt där programmerbara kretsar (FPGA) har nyckelfunktioner för att lösa krävande instrumenteringsuppgifter.

Den första projektet beskriver utveckling och implementering av en algoritm för detektering av partikelskurar efter partikelkollisioner i LHC-experimentets ATLAS-detektor. Experimentet genererar 40 miljoner händelser per sekund, som måste analyseras i real-tid med hjälp av snabba parallella algoritmer. Resultatet avgör vilka händelser som är tillräckligt intressanta för fortsatt noggrannare analys.

Den andra projektet beskriver utvecklingen av ett system som distribuerar klock- och trigger-signaler över ett 3 kilometers experimentområde med extrem precision, i den nya röntgenlaseracceleratorn XFEL vid DESY i Hamburg. Vid XFEL kommer man utforska nanostrukturer och till och med filma molekylers kemiska reaktioner.

I den tredje projektet beskrivs utvecklingen av ett höghastighets datainsamlingssystem, för segmenterade Ge-detektorer. Genom att översampla signalen med hög hastighet kan man uppnå en bättre noggrannhet i mätningen än vad AD-omvandlarens egna upplösning medger. Detta leder i sin tur  till förbättrade systemprestanda.

Slutligen beskrivs en innovativ lösning till ett test system för den elektronik, som Stockholms universitet har levererat till ATLAS detektorn. Det nya systemet ersätter det föregående testsystemet, som är baserad på föråldrade inte längre tillgängliga komponenter. Det nya systemet är dessutom också billigare eftersom det är baserat på ett standard FPGA utvecklingskort.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm University , 2011. , 99 p.
Keyword [en]
Instrumentation, Data acquisition, clock distribution, trigger, FPGA, PCB, LHC, ATLAS, XFEL
National Category
Other Physics Topics Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-64506ISBN: 978-91-7447-416-9 (print)OAI: oai:DiVA.org:su-64506DiVA: diva2:457982
Public defence
2011-12-15, sal FD5, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 10:30 (English)
Opponent
Supervisors
Projects
ATLAS experiment of the Large Hadron Collider experimentEuropean X-ray Free Electron Laser
Available from: 2011-11-24 Created: 2011-11-21 Last updated: 2011-12-20Bibliographically approved
List of papers
1. The ATLAS Level-1 Calorimeter Trigger Architecture
Open this publication in new window or tab >>The ATLAS Level-1 Calorimeter Trigger Architecture
2004 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 51, no 3, 356-360 p.Article in journal (Refereed) Published
Abstract [en]

The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/τ cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC timing, trigger and control system (TTC). A common data merger module (CMM) uses field-programmable gate arrays (FPGAs) with multiple configurations for summing electron/photon and τ/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquisition (DAQ) system, and region-of-interest (RoI) data to the level-2 triggers. Extensive use of FPGAs throughout the system makes the trigger flexible and upgradable, and several architectural choices have been made to reduce the number of intercrate links and make the hardware more robust.

National Category
Subatomic Physics
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64526 (URN)10.1109/TNS.2004.828800 (DOI)
Projects
ATLAS at LHC at CERN
Note
J. Garvey et al (39 authors)Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2017-12-08Bibliographically approved
2. ATLAS Level-1 Calorimeter Trigger: Subsystem Tests of a Jet/Energy-sum Processor Module
Open this publication in new window or tab >>ATLAS Level-1 Calorimeter Trigger: Subsystem Tests of a Jet/Energy-sum Processor Module
2004 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 51, no 5, 2356-2361 p.Article in journal (Refereed) Published
Abstract [en]

The ATLAS Level-1 Calorimeter Trigger consists of a Preprocessor, a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitized trigger-tower data from the Preprocessor and produce trigger multiplicities and total and missing energy for the final trigger decision. The trigger also provides region-of-interest information for the Level-2 trigger and intermediate results of the data acquisition system for monitoring and diagnostics by using Readout Driver modules. The JEP identifies and localizes jets, and sums total and missing transverse energy information from the trigger data. The Jet/Energy Module (JEM) is the main module of the JEP. The JEM prototype is designed to be functionally identical to the final production module for ATLAS and to have the full number of channels. Three JEM prototypes have been built and successfully tested. Various test vector patterns were used to test the energy summation and the jet algorithms. Data communication between adjacent JEMs and all other relevant modules of the JEP has been tested. Recent test results using the JEM prototypes are discussed.

National Category
Subatomic Physics
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64528 (URN)10.1109/TNS.2004.835693 (DOI)
Projects
ATLAS at LHC at CERN
Note
J. Garvey et al. (39 authors)Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2017-12-08Bibliographically approved
3. Pre-Production Validation of the ATLAS Level-1 Calorimeter Trigger System
Open this publication in new window or tab >>Pre-Production Validation of the ATLAS Level-1 Calorimeter Trigger System
2006 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 53, no 3, 859-863 p.Article in journal (Refereed) Published
Abstract [en]

The Level-1 Calorimeter Trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along with a description of the methodology used to perform the tests.

National Category
Subatomic Physics
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64529 (URN)10.1109/TNS.2006.874798 (DOI)
Projects
ATLAS at LHC at CERN
Note
R. Achenbach et al. (43 authors)Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2017-12-08Bibliographically approved
4. A System for Distributing High-Speed Synchronous High-Precision Clock and Trigger Data over Large Distances
Open this publication in new window or tab >>A System for Distributing High-Speed Synchronous High-Precision Clock and Trigger Data over Large Distances
Show others...
2008 (English)In: Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE, 2008, 2581-2584 p.Conference paper, Published paper (Refereed)
Abstract [en]

The distribution of precise timing throughout the European X-ray Free Electron Laser project [1] (XFEL) and its triggering system is a very challenging part of the system design. ADCs in data acquisition systems and DACs in control systems will require very high precision clocks. The clocks need to be synchronous to each other, both in frequency and phase, with a jitter performance better than 5 ps (RMS). At some high-speed ADCs it might even need a precision down to 0.1ps. The frequencies that must be available are the main 1.3 GHz and some frequencies below, which are all derived from the main frequency. The phase needs to be adjustable to allow synchronization between separate devices.

Keyword
Clocks, Electrons, Field programmable gate arrays, Frequency synchronization, Optical fiber cables, Physics, Power cables, Telephony, Timing, X-ray lasers
National Category
Accelerator Physics and Instrumentation Control Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64531 (URN)10.1109/NSSMIC.2008.4774885 (DOI)978-1-4244-2714-7 (ISBN)
Projects
European XFEL
Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2012-01-04Bibliographically approved
5. Timing and Triggering System Prototype for the XFEL Project
Open this publication in new window or tab >>Timing and Triggering System Prototype for the XFEL Project
2010 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 58, no 4, 1852-1856 p.Article in journal (Refereed) Published
Abstract [en]

The European X-ray Free Electron Laser (XFEL) [1] at DESY in Hamburg will begin operating in the next few years, enabling new, ground-breaking research opportunities. The entire system requires very precise clock and trigger distribution, synchronous with the 1.3 GHz system RF-frequency, over distances of more than 3.4 km. The new experiment demanded features that other commercial solutions could not yet provide. Researchers at Stockholm University and DESY have developed a prototype for the timing system of XFEL. It has been decided that XFEL will use modern ATCA and Micro-TCA systems because of their advanced features and reliability. The timing system has been adapted to the Micro-TCA bus standard and also follows the new upcoming xTCA for physics standard. The prototype is fully functional and complete. It will serve as a platform for future development of the whole timing system. This paper describes the hardware design and some test results using the prototype board.

National Category
Accelerator Physics and Instrumentation Control Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64534 (URN)10.1109/TNS.2011.2151205 (DOI)000293975700067 ()
Projects
European XFEL
Note
authorCount :4Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2017-12-08Bibliographically approved
6. An Advanced FPGA Based Phase-Lock-Loop System as an Alternative Solution for the XFEL Timing System
Open this publication in new window or tab >>An Advanced FPGA Based Phase-Lock-Loop System as an Alternative Solution for the XFEL Timing System
2009 (English)In: Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE, 2009, 1871-1872 p.Conference paper, Published paper (Refereed)
Abstract [en]

The European XFEL project requires a high-speed, very precise clock and timing distribution over large distances. A prototype system which fulfils current requirements that uses high-end components has just been completed and is being tested. However, the system is quite complicated and the boards are very complex, being designed using the small micro-TCA form factor. A way to simplify the system, and perhaps reduce cost, would be to implement an Advanced PLL in the programmable logic of an FPGA, which then would control an external VCO. By doing so several major issues could be resolved at the same time, while making more use of the advanced features of modern FPGAs. Such a system could be an alternative solution to the complex part of the Timing and Triggering System for XFEL.

Keyword
Clocks, Costs, Field programmable gate arrays, Phase locked loops, Programmable control, Programmable logic arrays, Programmable logic devices, Prototypes, System testing, Timing
National Category
Accelerator Physics and Instrumentation Control Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:su:diva-64536 (URN)10.1109/NSSMIC.2009.5402175 (DOI)978-1-4244-3961-4 (ISBN)
Projects
European XFEL
Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2012-01-04Bibliographically approved
7. A High-Speed Data Acquisition System for Segmented Ge-Detectors
Open this publication in new window or tab >>A High-Speed Data Acquisition System for Segmented Ge-Detectors
Show others...
2006 (English)In: Nuclear Science Symposium Conference Record. IEEE, 2006, Vol. 1, 999-1001 p.Conference paper, Published paper (Refereed)
Abstract [en]

When using segmented Ge-detectors for gamma ray tracking it is necessary to determine the segment pulse shapes with high accuracy. A high-speed data acquisition system with many channels, high precision and with high sampling rate is required. To find the optimum performance, we are investigating what can be achieved by a system with extremely high sampling rates, 10 bits @2 GS/s. There are many other applications for such a system. Higher sampling rates usually mean lower bit resolution of the ADC, but with oversampling we expect to achieve a very good energy and time resolution. The system uses high performance FPGAs (Xilinx Virtex-IV) to cope with the data rates delivered by the high speed ADCs and to make all the data processing onboard in real time. Control and monitoring is implemented in an embedded soft processor. This processor is also in charge of the offboard gigabit Ethernet communication. The final system will consist of several separate boards, each with a number of input channels that will have to communicate with each other in real time over a high-speed communication link. The processed result will be transmitted over Ethernet to final storage. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are: the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.

National Category
Subatomic Physics Signal Processing Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64772 (URN)10.1109/NSSMIC.2006.356014 (DOI)1-4244-0560-2 (ISBN)
Available from: 2011-11-23 Created: 2011-11-23 Last updated: 2012-01-04Bibliographically approved
8. A High-Speed Data Acquisition System for Segmented Ge-Detectors
Open this publication in new window or tab >>A High-Speed Data Acquisition System for Segmented Ge-Detectors
Show others...
2007 (English)In: Nuclear Science Symposium Conference Record. IEEE, 2007, Vol. 1, 536-537 p.Conference paper, Published paper (Refereed)
Abstract [en]

When using segmented Ge-detectors for gamma ray tracking it is necessary to determine the segment pulse shapes with high accuracy. A high-speed data acquisition system with many channels, high precision and with high sampling rate is required. There are also many other applications for such a system. Our system uses high performance FPGAs (Xilinx Virtex-V [2]) to cope with the data rates delivered by the high speed ADC chosen (Atmel 2Gsps, 10 bits) and to make all the data processing onboard in real time. Each board contains four such ADCs, which can either handle four channels up to full speed, or achieve higher sampling rates with interleaving. The boards can communicate with each other over different types of high-speed communication links. Control and monitoring is implemented with embedded processors. The processed result will be transmitted over Ethernet to final storage. The project introduces many challenging issues: signal integrity, ADC performance, interfacing ADCs to the FPGA, synchronisation of ADCs across the entire system, implementing flexible processing algorithms, high speed interconnection between boards and managing the significant heat generation. This is an ongoing project with interesting potentials for the future.

National Category
Subatomic Physics Signal Processing Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64539 (URN)10.1109/NSSMIC.2007.4436387 (DOI)978-1-4244-0922-8 (ISBN)
Available from: 2011-11-21 Created: 2011-11-21 Last updated: 2012-01-04Bibliographically approved
9. A Small Portable Test System for the TileCal Digitizer System
Open this publication in new window or tab >>A Small Portable Test System for the TileCal Digitizer System
2008 (English)Conference paper, Poster (with or without abstract) (Refereed)
Abstract [en]

The hadronic Tile Calorimeter (TileCal) of the ATLAS detector at LHC has a digitization, pipeline and readout system composed of nearly 2000 boards [1][2], developed and maintained by Stockholm University. Prior to now a rather complex test system been used to verify the functionality of the boards. However this system was developed nearly 10 years ago and now difficult to maintain due to several already obsolete components. A new, simpler, more reliable, and portable test system was therefore initiated. Its components have been chosen to reduce problems with obsolescence, and to allow easy migration to new platforms over the lifetime of the digitizer system.

National Category
Subatomic Physics Control Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-64540 (URN)
Conference
TWEPP-08 Topical Workshop on Electronics for Particle Physics, 15-19 September 2008, Naxos, Greece
Projects
ATLAS at LHC at CERN
Available from: 2011-11-22 Created: 2011-11-21 Last updated: 2012-07-10Bibliographically approved

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