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Optimizing latency in Xilinx FPGA implementations of the GBT
Stockholm University, Faculty of Science, Department of Physics.
Stockholm University, Faculty of Science, Department of Physics.
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2010 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 5, C12017Article in journal (Refereed) Published
Abstract [en]

The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

Place, publisher, year, edition, pages
2010. Vol. 5, C12017
Keyword [en]
Optical detector readout concepts, Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases)
National Category
Physical Sciences
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-66240DOI: 10.1088/1748-0221/5/12/C12017ISI: 000287858300018OAI: oai:DiVA.org:su-66240DiVA: diva2:467419
Conference
Topical Workshop on Electronics for Particle Physics, Aachen, Germany, Sep 20-24, 2010
Note

authorCount :5

Available from: 2011-12-19 Created: 2011-12-19 Last updated: 2017-12-08Bibliographically approved
In thesis
1. Readout link and control board for the ATLAS Tile Calorimeter upgrade
Open this publication in new window or tab >>Readout link and control board for the ATLAS Tile Calorimeter upgrade
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The Large Hadron Collider (LHC) at the CERN laboratory was designed to study the elementary particles and forces and search for new physics.  Detectors at LHC were designed to observe proton-proton collisions with center of mass energies up to 14 TeV, seven times higher than previously possible. One of the largest of these is the general purpose detector ATLAS. After almost 20 years of planning and construction, LHC and its detectors were finished in 2008. Since then ATLAS has produced valuable data, which contributed to the discovery of the 1964 postulated Higgs-particle and thus to the Nobel prize in physics in 2013. To expand the searches, LHC and its detectors will undergo several upgrades to the increase luminosity at least by a factor of 5 and to exploit the full potential of the machine. In order to adapt the detector to the resulting increasing event rates and radiation levels, new electronics have to be developed.

This thesis describes the development process of a new upgraded digital readout system for one of the sub-detectors in ATLAS, the scintillating Tile Calorimeter (TileCal), and more specifically one of its key components, the high-speed data link DaughterBoard. Starting from the idea of transferring all recorded information of the detector using high speed serial optical links and the concept of using re-programmable logic for the readout electronics, completely new on-detector electronics were designed to be used as a core component for communication, control and monitoring. The electronics was tested, electrical characterized and proven to work in a setup similar to the upgraded readout electronics. The DaughterBoard is the Stockholm University contribution to the ATLAS upgrade in 2023.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm Univeristy, 2015. 111 p.
Keyword
Digital electronics, FPGA, Data acquisition, Detector readout
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-116258 (URN)978-91-7649-177-5 (ISBN)
Public defence
2015-05-28, sal FB42, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 13:00 (English)
Opponent
Supervisors
Available from: 2015-05-06 Created: 2015-04-16 Last updated: 2015-06-24Bibliographically approved

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