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High Performance FPGA-Based DMA Interface for PCIe
Stockholm University, Faculty of Science, Department of Physics.
Stockholm University, Faculty of Science, Department of Physics.
Stockholm University, Faculty of Science, Department of Physics.
2014 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 61, no 2, 745-749 p.Article in journal (Refereed) Published
Abstract [en]

We present a data communication suite developed for use in the Track Engine Trigger for the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-FPGA memory modules and FIFOs. The DMA which is based on the Xilinx' bus master DMA, produces measured transfer speeds up to 748 MB/s (read) and 784 MB/s (write) using the Xilinx VC707 Virtex-7 board. The hardware part of the suite has been verified on different circuit boards with different FPGAs.

Place, publisher, year, edition, pages
2014. Vol. 61, no 2, 745-749 p.
Keyword [en]
Data acquisition, data communication, data transfer, FPGA, linux, readout electronics, trigger
National Category
Physical Sciences
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-104562DOI: 10.1109/TNS.2014.2304691ISI: 000334931100006OAI: oai:DiVA.org:su-104562DiVA: diva2:724612
Note

AuthorCount:3;

Available from: 2014-06-13 Created: 2014-06-11 Last updated: 2017-12-05Bibliographically approved
In thesis
1. Readout link and control board for the ATLAS Tile Calorimeter upgrade
Open this publication in new window or tab >>Readout link and control board for the ATLAS Tile Calorimeter upgrade
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The Large Hadron Collider (LHC) at the CERN laboratory was designed to study the elementary particles and forces and search for new physics.  Detectors at LHC were designed to observe proton-proton collisions with center of mass energies up to 14 TeV, seven times higher than previously possible. One of the largest of these is the general purpose detector ATLAS. After almost 20 years of planning and construction, LHC and its detectors were finished in 2008. Since then ATLAS has produced valuable data, which contributed to the discovery of the 1964 postulated Higgs-particle and thus to the Nobel prize in physics in 2013. To expand the searches, LHC and its detectors will undergo several upgrades to the increase luminosity at least by a factor of 5 and to exploit the full potential of the machine. In order to adapt the detector to the resulting increasing event rates and radiation levels, new electronics have to be developed.

This thesis describes the development process of a new upgraded digital readout system for one of the sub-detectors in ATLAS, the scintillating Tile Calorimeter (TileCal), and more specifically one of its key components, the high-speed data link DaughterBoard. Starting from the idea of transferring all recorded information of the detector using high speed serial optical links and the concept of using re-programmable logic for the readout electronics, completely new on-detector electronics were designed to be used as a core component for communication, control and monitoring. The electronics was tested, electrical characterized and proven to work in a setup similar to the upgraded readout electronics. The DaughterBoard is the Stockholm University contribution to the ATLAS upgrade in 2023.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm Univeristy, 2015. 111 p.
Keyword
Digital electronics, FPGA, Data acquisition, Detector readout
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-116258 (URN)978-91-7649-177-5 (ISBN)
Public defence
2015-05-28, sal FB42, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 13:00 (English)
Opponent
Supervisors
Available from: 2015-05-06 Created: 2015-04-16 Last updated: 2015-06-24Bibliographically approved

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