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Readout link and control board for the ATLAS Tile Calorimeter upgrade
Stockholm University, Faculty of Science, Department of Physics. (Instrumenteringsfysik)
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The Large Hadron Collider (LHC) at the CERN laboratory was designed to study the elementary particles and forces and search for new physics.  Detectors at LHC were designed to observe proton-proton collisions with center of mass energies up to 14 TeV, seven times higher than previously possible. One of the largest of these is the general purpose detector ATLAS. After almost 20 years of planning and construction, LHC and its detectors were finished in 2008. Since then ATLAS has produced valuable data, which contributed to the discovery of the 1964 postulated Higgs-particle and thus to the Nobel prize in physics in 2013. To expand the searches, LHC and its detectors will undergo several upgrades to the increase luminosity at least by a factor of 5 and to exploit the full potential of the machine. In order to adapt the detector to the resulting increasing event rates and radiation levels, new electronics have to be developed.

This thesis describes the development process of a new upgraded digital readout system for one of the sub-detectors in ATLAS, the scintillating Tile Calorimeter (TileCal), and more specifically one of its key components, the high-speed data link DaughterBoard. Starting from the idea of transferring all recorded information of the detector using high speed serial optical links and the concept of using re-programmable logic for the readout electronics, completely new on-detector electronics were designed to be used as a core component for communication, control and monitoring. The electronics was tested, electrical characterized and proven to work in a setup similar to the upgraded readout electronics. The DaughterBoard is the Stockholm University contribution to the ATLAS upgrade in 2023.

Place, publisher, year, edition, pages
Stockholm: Department of Physics, Stockholm Univeristy , 2015. , 111 p.
Keyword [en]
Digital electronics, FPGA, Data acquisition, Detector readout
National Category
Physical Sciences
Research subject
Physics
Identifiers
URN: urn:nbn:se:su:diva-116258ISBN: 978-91-7649-177-5 (print)OAI: oai:DiVA.org:su-116258DiVA: diva2:805818
Public defence
2015-05-28, sal FB42, AlbaNova universitetscentrum, Roslagstullsbacken 21, Stockholm, 13:00 (English)
Opponent
Supervisors
Available from: 2015-05-06 Created: 2015-04-16 Last updated: 2015-06-24Bibliographically approved
List of papers
1. An FPGA based backup version of the TileCal Digitizer
Open this publication in new window or tab >>An FPGA based backup version of the TileCal Digitizer
2010 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 5, C11020Article in journal (Refereed) Published
Abstract [en]

The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

Keyword
Radiation-hard electronics, Front-end electronics for detector readout, Data acquisition circuits
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-116248 (URN)10.1088/1748-0221/5/11/C11020 (DOI)
Available from: 2015-04-16 Created: 2015-04-16 Last updated: 2017-12-04Bibliographically approved
2. Optimizing latency in Xilinx FPGA implementations of the GBT
Open this publication in new window or tab >>Optimizing latency in Xilinx FPGA implementations of the GBT
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2010 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 5, C12017Article in journal (Refereed) Published
Abstract [en]

The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

Keyword
Optical detector readout concepts, Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases)
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-66240 (URN)10.1088/1748-0221/5/12/C12017 (DOI)000287858300018 ()
Conference
Topical Workshop on Electronics for Particle Physics, Aachen, Germany, Sep 20-24, 2010
Note

authorCount :5

Available from: 2011-12-19 Created: 2011-12-19 Last updated: 2017-12-08Bibliographically approved
3. High Performance FPGA-Based DMA Interface for PCIe
Open this publication in new window or tab >>High Performance FPGA-Based DMA Interface for PCIe
2014 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 61, no 2, 745-749 p.Article in journal (Refereed) Published
Abstract [en]

We present a data communication suite developed for use in the Track Engine Trigger for the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-FPGA memory modules and FIFOs. The DMA which is based on the Xilinx' bus master DMA, produces measured transfer speeds up to 748 MB/s (read) and 784 MB/s (write) using the Xilinx VC707 Virtex-7 board. The hardware part of the suite has been verified on different circuit boards with different FPGAs.

Keyword
Data acquisition, data communication, data transfer, FPGA, linux, readout electronics, trigger
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-104562 (URN)10.1109/TNS.2014.2304691 (DOI)000334931100006 ()
Note

AuthorCount:3;

Available from: 2014-06-13 Created: 2014-06-11 Last updated: 2017-12-05Bibliographically approved
4. A prototype for the upgraded readout electronics of TileCal
Open this publication in new window or tab >>A prototype for the upgraded readout electronics of TileCal
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2012 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 7, C02006Article in journal (Refereed) Published
Abstract [en]

Upgrade plans for the ATLAS hadronic tile calorimeter (TileCal) at the LHC include full granularity readout to the 1st level trigger. R&D activities at different laboratories target different parts of the upgraded system. We are developing a possible implementation of the future readout electronics to be included in a full functional demonstrator. This must be capable of adapting to each of the three different front-end alternatives being considered. Prototypes of the two PCBs that will be in charge of digitization, control and communication have been developed. The design is redundant and uses FPGAs with fault tolerant firmware for control and protocol conversion. Communication and clock synchronization between on and offdetector electronics is implemented via high speed optical links using the GBT protocol.

Keyword
Analogue electronic circuits, Front-end electronics for detector readout, Digital electronic circuits
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-80134 (URN)10.1088/1748-0221/7/02/C02006 (DOI)000303940900006 ()
Note

AuthorCount:7;

Available from: 2012-09-18 Created: 2012-09-12 Last updated: 2017-12-07Bibliographically approved
5. An Early Slice Prototype for the Upgraded Readout Electronics of TileCal
Open this publication in new window or tab >>An Early Slice Prototype for the Upgraded Readout Electronics of TileCal
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2011 (English)In: Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE, IEEE Robotics and Automation Society, 2011, 836-840 p.Conference paper, Published paper (Refereed)
Abstract [en]

We have developed a slice prototype of the full TileCal readout chain based on prototype modules and off-the-shelf components. As different module prototypes are developed and become available they can replace earlier prototypes or emulators in the chain. Due to its modular and flexible structure, the prototype can adapt to changing requirements. This will allow most of the final functionality to be developed and tested before the hardware design is finalized.

Place, publisher, year, edition, pages
IEEE Robotics and Automation Society, 2011
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-116257 (URN)10.1109/NSSMIC.2011.6154550 (DOI)978-1-4673-0118-3 (ISBN)
Conference
IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), Valencia, October 23-29, 2011
Available from: 2015-04-16 Created: 2015-04-16 Last updated: 2015-04-16Bibliographically approved
6. Development of a readout link board for the demonstrator of the ATLAS Tile calorimeter upgrade
Open this publication in new window or tab >>Development of a readout link board for the demonstrator of the ATLAS Tile calorimeter upgrade
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2013 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 8, C03025Article in journal (Refereed) Published
Abstract [en]

A hybrid readout system is being developed for installation in one module of the ATLAS scintillating Tile Calorimeter (TileCal) during the long LHC shutdown in 2013/2014. The hybrid combines a fully functional demonstrator of the full-digital system planned for installation in 2022 with circuitry to maintain compatibility with the existing system. This is the report on a second generation prototype link and controller board connecting the on-and off-detector electronics. The main logic component within this board is a XILINX Kintex-7 FPGA connected to an 12x5 Gbps SNAP12 opto transmitter and a 4x10 Gbps QSFP+ connector, for off-detector communication. One of the latter two will be chosen for the final design.

Keyword
Front-end electronics for detector readout, Optical detector readout concepts
National Category
Accelerator Physics and Instrumentation
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-89727 (URN)10.1088/1748-0221/8/03/C03025 (DOI)000316990700025 ()
Conference
Topical Workshop on Electronics for Particle Physics, Oxford, England, Sep 17-21, 2012
Note

AuthorCount:6;

Available from: 2013-05-08 Created: 2013-05-06 Last updated: 2017-12-06Bibliographically approved
7. Development of a digital readout board for the ATLAS Tile Calorimeter upgrade demonstrator
Open this publication in new window or tab >>Development of a digital readout board for the ATLAS Tile Calorimeter upgrade demonstrator
Show others...
2014 (English)In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 9, C01001Article in journal (Refereed) Published
Abstract [en]

During the LHC shutdown in 2013/14, one of the ATLAS scintillating Tile Calorimeter (TileCal) on-detector modules will be replaced with a compatible hybrid demonstrator system. This is being built to fulfill all requirements for the complete upgrade of the TileCal electronics in 2022 but augmented to stay compatible with the present system. We report on the hybrid system's FPGA based communication module that is responsible for receiving and unpacking commands using a 4.8 Gbps downlink and driving a high bandwidth data uplink. The report includes key points like multi-gigabit transmission, clock distribution, programming and operation of the hardware. We also report on a firmware skeleton implementing all these key points and demonstrate how timing, trigger, control and data transmission can be achieved in the demonstrator.

Keyword
Optical detector readout concepts, Front-end electronics for detector readout
National Category
Physical Sciences
Research subject
Physics
Identifiers
urn:nbn:se:su:diva-102505 (URN)10.1088/1748-0221/9/01/C01001 (DOI)000332307000001 ()
Conference
Topical Workshop on Electronics for Particle Physics, Perugia, Italy, Sep 23-27, 2013
Note

AuthorCount:6;

Available from: 2014-04-07 Created: 2014-04-07 Last updated: 2017-12-05Bibliographically approved

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  • modern-language-association-8th-edition
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  • nn-NO
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Output format
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