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  • 1.
    Eriksson, Daniel
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Muschter, Steffen
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Anderson, K.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Kavianipour, Hossein
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Oreglia, M.
    Tang, F.
    A prototype for the upgraded readout electronics of TileCal2012Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 7, artikkel-id C02006Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Upgrade plans for the ATLAS hadronic tile calorimeter (TileCal) at the LHC include full granularity readout to the 1st level trigger. R&D activities at different laboratories target different parts of the upgraded system. We are developing a possible implementation of the future readout electronics to be included in a full functional demonstrator. This must be capable of adapting to each of the three different front-end alternatives being considered. Prototypes of the two PCBs that will be in charge of digitization, control and communication have been developed. The design is redundant and uses FPGAs with fault tolerant firmware for control and protocol conversion. Communication and clock synchronization between on and offdetector electronics is implemented via high speed optical links using the GBT protocol.

  • 2.
    Eriksson, Daniel
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Muschter, Steffen
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    An FPGA based backup version of the TileCal Digitizer2010Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 5, artikkel-id C11020Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

  • 3.
    Kavianipour, Hossein
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Muschter, Steffen
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    High Performance FPGA-Based DMA Interface for PCIe2014Inngår i: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 61, nr 2, s. 745-749Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    We present a data communication suite developed for use in the Track Engine Trigger for the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-FPGA memory modules and FIFOs. The DMA which is based on the Xilinx' bus master DMA, produces measured transfer speeds up to 748 MB/s (read) and 784 MB/s (write) using the Xilinx VC707 Virtex-7 board. The hardware part of the suite has been verified on different circuit boards with different FPGAs.

  • 4.
    Muschter, Steffen
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Anderson, K.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Eriksson, Daniel
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Oreglia, M.
    Tang, F.
    Development of a readout link board for the demonstrator of the ATLAS Tile calorimeter upgrade2013Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 8, artikkel-id C03025Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A hybrid readout system is being developed for installation in one module of the ATLAS scintillating Tile Calorimeter (TileCal) during the long LHC shutdown in 2013/2014. The hybrid combines a fully functional demonstrator of the full-digital system planned for installation in 2022 with circuitry to maintain compatibility with the existing system. This is the report on a second generation prototype link and controller board connecting the on-and off-detector electronics. The main logic component within this board is a XILINX Kintex-7 FPGA connected to an 12x5 Gbps SNAP12 opto transmitter and a 4x10 Gbps QSFP+ connector, for off-detector communication. One of the latter two will be chosen for the final design.

  • 5.
    Muschter, Steffen
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Anderson, Kelby
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Eriksson, Daniel
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Kavianipour, Hossein
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Oreglia, Mark
    Tang, Fukun
    An Early Slice Prototype for the Upgraded Readout Electronics of TileCal2011Inngår i: Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE, IEEE Robotics and Automation Society, 2011, s. 836-840Konferansepaper (Fagfellevurdert)
    Abstract [en]

    We have developed a slice prototype of the full TileCal readout chain based on prototype modules and off-the-shelf components. As different module prototypes are developed and become available they can replace earlier prototypes or emulators in the chain. Due to its modular and flexible structure, the prototype can adapt to changing requirements. This will allow most of the final functionality to be developed and tested before the hardware design is finalized.

  • 6.
    Muschter, Steffen
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Baron, S.
    Bohm, Christian
    Cachemiche, J. -P
    Soos, C.
    Erratum: Optimizing latency in Xilinx FPGA implementations of the GBT2011Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 6, artikkel-id E05001Artikkel i tidsskrift (Annet vitenskapelig)
  • 7.
    Muschter, Steffen
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Baron, S.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Cachemiche, J. -P
    Soos, C.
    Optimizing latency in Xilinx FPGA implementations of the GBT2010Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 5, artikkel-id C12017Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  • 8.
    Muschter, Steffen Lothar
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Readout link and control board for the ATLAS Tile Calorimeter upgrade2015Doktoravhandling, med artikler (Annet vitenskapelig)
    Abstract [en]

    The Large Hadron Collider (LHC) at the CERN laboratory was designed to study the elementary particles and forces and search for new physics.  Detectors at LHC were designed to observe proton-proton collisions with center of mass energies up to 14 TeV, seven times higher than previously possible. One of the largest of these is the general purpose detector ATLAS. After almost 20 years of planning and construction, LHC and its detectors were finished in 2008. Since then ATLAS has produced valuable data, which contributed to the discovery of the 1964 postulated Higgs-particle and thus to the Nobel prize in physics in 2013. To expand the searches, LHC and its detectors will undergo several upgrades to the increase luminosity at least by a factor of 5 and to exploit the full potential of the machine. In order to adapt the detector to the resulting increasing event rates and radiation levels, new electronics have to be developed.

    This thesis describes the development process of a new upgraded digital readout system for one of the sub-detectors in ATLAS, the scintillating Tile Calorimeter (TileCal), and more specifically one of its key components, the high-speed data link DaughterBoard. Starting from the idea of transferring all recorded information of the detector using high speed serial optical links and the concept of using re-programmable logic for the readout electronics, completely new on-detector electronics were designed to be used as a core component for communication, control and monitoring. The electronics was tested, electrical characterized and proven to work in a setup similar to the upgraded readout electronics. The DaughterBoard is the Stockholm University contribution to the ATLAS upgrade in 2023.

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  • 9.
    Muschter, Steffen
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Åkerstedt, Henrik
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Anderson, K.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Oreglia, M.
    Tang, F.
    Development of a digital readout board for the ATLAS Tile Calorimeter upgrade demonstrator2014Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 9, artikkel-id C01001Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    During the LHC shutdown in 2013/14, one of the ATLAS scintillating Tile Calorimeter (TileCal) on-detector modules will be replaced with a compatible hybrid demonstrator system. This is being built to fulfill all requirements for the complete upgrade of the TileCal electronics in 2022 but augmented to stay compatible with the present system. We report on the hybrid system's FPGA based communication module that is responsible for receiving and unpacking commands using a 4.8 Gbps downlink and driving a high bandwidth data uplink. The report includes key points like multi-gigabit transmission, clock distribution, programming and operation of the hardware. We also report on a firmware skeleton implementing all these key points and demonstrate how timing, trigger, control and data transmission can be achieved in the demonstrator.

  • 10. Tang, F.
    et al.
    Åkerstedt, Henrik
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Anderson, K.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Hildebrand, K.
    Muschter, Steffen
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Oreglia, M.
    Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator2015Inngår i: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 62, nr 3, s. 1045-1049Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The TileCal Demonstrator is a prototype for the future upgrade of the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals and can communicate as the present system. The on-detector part of the Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Analog Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. It is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and detector operation monitoring. We plan to insert one fully functional Demonstrator module into the present ATLAS TileCal detector for the LHC RUN 2 in Christmas shutdown in 2015 or 2016.

  • 11.
    Åkerstedt, Henrik
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Muschter, Steffen
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Silverstein, Samuel B.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Valdés, Eduardo
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    A radiation tolerant Data link board for the ATLAS Tile Cal upgrade2016Inngår i: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 11, artikkel-id C01074Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper describes the latest, full-functionality revision of the high-speed data link board developed for the Phase-2 upgrade of ATLAS hadronic Tile Calorimeter. The link board design is highly redundant, with digital functionality implemented in two Xilinx Kintex-7 FPGAs, and two Molex QSFP+ electro-optic modules with uplinks run at 10 Gbps. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The redundant design eliminates virtually all single-point error modes, and a combination of triple-mode redundancy (TMR), internal and external scrubbing will provide adequate protection against radiation-induced errors. The small portion of the FPGA design that cannot be protected by TMR will be the dominant source of radiation-induced errors, even if that area is small.

  • 12.
    Åkerstedt, Henrik
    et al.
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Muschter, Steffen
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Drake, Gary
    Anderson, Kelby
    Bohm, Christian
    Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum.
    Oreglia, Mark
    Tang, Fukun
    Reliable and Redundant FPGA Based Read-Out Design in the ATLAS TileCal Demonstrator2015Inngår i: IEEE Transactions on Nuclear Science, ISSN 0018-9499, E-ISSN 1558-1578, Vol. 62, nr 5, s. 2129-2133Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The current ATLAS Tile Calorimeter read-out system is scheduled for replacement around 2023 due to old age and higher performance needs. The new proposed system is designed to be radiation tolerant, modular, redundant and reconfigurable. To achieve full detector read-out, Kintex-7 FPGAs from Xilinx will be used, in addition to multiple 10 Gb/s optical read-out links. During 2015/2016, a hybrid demonstrator system including the new read-out system will be installed in one slice of the ATLAS Tile Calorimeter to evaluate the new design. This paper describes different firmware strategies along with their integration in the demonstrator in the context of high reliability protection against hardware malfunction and radiation induced errors.

1 - 12 of 12
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