The Phase-II upgrade plan for the ATLAS Hadronic Tile Calorimeter facing the High-Luminosity LHC (HL-LHC) era includes approximately 1000 radiation tolerant read-out link and control boards (Daughterboards) that will provide full-granularity digital data to a fully-digital trigger system off-detector through multi-Gbps optic fibres. Different Daughterboard (DB) revisions have been developed, each successively aiming to meet the demanding HL-LHC requirements. The DB communicates with the off-detector systems via four 9.6 Gbps uplinks and two 4.8 Gbps downlinks. The DB performs high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC-synchronous timing to the front-end system. The design aims to minimize radiation-induced errors and enhance data reliability by embracing a fully double redundant design using CERN radiation hard GBTx ASICs and Xilinx FPGAs, implementing Triple Mode Redundancy (TMR), adopting Soft Error Mitigation (SEM) to correct for configuration memory Single Event Upsets (SEU), and employing Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) in the data format of the uplink and downlink, respectively. Total Ionizing Dose (TID), Non-Ionizing Energy Losses (NIEL) and Single Event Effects (SEE) radiation tests have been performed in order to assess the radiation tolerance strategies followed in the design and to qualify the DB for the HL-LHC requirements according to the ATLAS policy on radiation tolerant electronics. This thesis presents the author's contribution to the development of the DB through the different revisions, the integration of the DB to the Demonstrator and the radiation tests performed aiming to demonstrate the readiness of the DB to withstand the radiation requirements imposed by the HL-LHC. Resulting of this document, the author proposes strategies to be used in the new DB design moving forward the final design to be produced and inserted in ATLAS during the 2024-2026 period.